Verilog
From HvWiki
Verilog is a Hardware Description Language (HDL) used to model electronic systems. The language (sometimes called Verilog HDL) supports the design, testing, and implementation of analog, digital, and mixed-signal circuits at various levels of abstraction.
The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted. The language has a pre-processor like C, and the major control keywords such as "if", "while", etc are similar. The formatting mechanism in the printing routines and language operators (and their precedence) are also similar.
See also VHDL.
